Professor Lin and his students have published more than 100 articles in the areas of electronic design automation and integrated circuit designs. Most of them are archived in IEEE Xplore and ACM Digital Library.

2022~present        Dean, College of Informatics, Yuan Ze University.

2008-present        Professor, Department of Computer Science and Engineering, Yuan Ze University, Chung-Li, 320 Taiwan.

2017-2022               Director, International Program in Informatics for Bachelor, Yuan Ze University, Chung-Li, 320 Taiwan

2011-2017                 Head, Department of Computer Science and Engineering, Yuan Ze University, Chung-Li, 320 Taiwan

1995-2008              Associate Professor, Department of Computer Science and Engineering, Yuan Ze University, Chung-Li, 320 Taiwan.

1994-1995               Research Associate, Application and Research Center of Information Technology, Tatung Institute of Technology, Taipei.

1992-1994               Research and Development Staff, Large Scale Computing Division, IBM, Poughkeepsie, New York, USA. 

1986-1987               Research Assistant, ITRI, Hsin-Chu, Taiwan.

VLSI/CAD Laboratory was established in 1995. It focuses on developing algorithms (software) and design methodologies for Electronic Design Automation (EDA) of integrated circuits (or Computer-Aided VLSI Design). Due to the amazing advancement of semiconductor technologies, billions of transistors can be placed in a single chip. This enables us to design very powerful servers for cloud computing and networking and various products such as desktop PCs, HD TV, mobile phones, tablet PCs, notebooks, video/digital cameras,  and other smart electronic devices. One of the enabling technologies of designing chips for these products is Electronic Design Automation (EDA). EDA software (tools) can be used to solve the problems encountered during synthesizing, analyzing, verifying and testing a circuit. We are seeking more powerful algorithms and design methodologies for solving these problems to minimize chip size and power consumption while optimizing chip performance. Currently, we especially focus on the problems related to standard cell layouts and library development, power minimization, timing performance optimization, manufacturing yield optimization, etc.

To participate in our research work, one should be at least a senior student or preferably a master/Ph.D. student who majors in computer science and engineering or electrical and electronic engineering.