National Yang Ming Chiao Tung University

Emerging Device Technologies Lab

Girish Pahwa
https://edtech.web.nycu.edu.tw/

Research Field

Microelectronic Engineering

Introduction

Girish Pahwa currently serves as an assistant professor at the International College of Semiconductor Technology at National Yang Ming Chiao Tung University. Girish’s research primarily focuses on the device modeling, simulation, and device-circuit co-design of emerging nanoscale technologies. Prior to this role, Girish held positions as an assistant professional researcher in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley. During his tenure there, he notably served as the executive director of the Berkeley Device Modeling Center (BDMC) from March 2022 to February 2024, and as the center manager of the BDMC and BSIM (Berkeley Short Channel IGFET model) group from December 2020 to February 2023. He also contributed as a postdoctoral scholar and research & development engineer in the EECS department, at UC Berkeley from May 2020 to February 2023.

Girish earned his Ph.D. and master’s degrees in electrical engineering from the Indian Institute of Technology (IIT) Kanpur in 2020, following his bachelor’s degree in electronics and communication engineering from Delhi Technological University in 2014.

At the BDMC, Girish played a pivotal role in advancing the BSIM suite of compact models as the industry-standard tools for IC simulation and design in emerging applications. His work extends to the development of the first industry-standard cryogenic FinFET and FDSOI compact models, essential for the design of ICs relevant to quantum computing and cold electronics. He also developed ferroelectric device models and contributed extensively to the physics and device-circuit co-design strategies of these emerging devices that can potentially reduce CMOS power consumption many folds or enable computing in memory for artificial intelligence or other applications. He has also made significant contributions in developing industry-standard models for Thin Film Transistors and high-voltage MOSFETs, crucial for display and 3D BEOL integration, and power IC applications, respectively.

Girish is an active member of professional organizations such as the Institute of Electrical and Electronics Engineers (IEEE) and the Electron Devices Society (EDS). He serves as a reviewer for several journals and has over 65 technical publications in renowned journals and conferences. His contributions have been recognized with the IEEE EDS Early Career Award 2022, the Outstanding Ph.D. thesis award from IIT Kanpur in 2020, and the best paper award at the IEEE International Conference on Emerging Electronics (ICEE) in Mumbai, India, in 2016.

At the EDTech lab, we dive into the intricate world of emerging semiconductor technologies, unraveling the answers to fundamental device physics, modeling, and design problems.


Research Topics
  1. Compact Modeling and Simulation, Numerical Modeling
  2. Device Circuit Co-Design and Benchmarking of Emerging Semiconductor Technologies
  3. Ferroelectric Devices for Logic and Memory
  4. Cryogenic-CMOS for Quantum Computing and High-Performance Computing
  5. Oxide Semiconductor FETs for 3D BEOL and Display
  6. High Voltage MOSFETs
  7. III-V Technologies for RF

Honor
  • Selected as a member of IEEE EDS Electronic Materials Committee, 2024.
  • Technical program committee member of DTCO/STCO track at IEEE Electron Device Technology and Manufacturing (EDTM) Conference, 2024.
  • Selected as a Member of IEEE EDS Compact Modeling Committee, 2024.
  • IEEE Electron Device Society (EDS) Early Career Award, by IEEE EDS, 2022: This is one of the highest honors of IEEE EDS and recognizes early career technical development within the EDS’s field of interest.
  • Outstanding Ph.D. Thesis Award by IIT Kanpur, 2020.
  • Best Paper Award at IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, 2016 for the paper titled “Energy-Delay Tradeoffs in Negative Capacitance FinFET based CMOS Circuits”.
  • Panellist for IEEE EDS Networking Event for young professionals held on Nov 2, 2022.
  • Invited for IEEE EDS Webinar on “Compact Modeling of Emerging Ferroelectric Devices”, held on Nov 30, 2022.
  • Best Presentation Award (co-author), at IEEE International Conference on Emerging Electronics (ICEE), 2018, for the paper on “Compact Modeling of Drain Current in Double Gate Negative Capacitance MFIS Transistor”.
  • Reviewer of the following journals: IEEE Electron Device Letters (appeared in golden list of the reviewers from 2017-2022), IEEE Transactions on Electron Devices (appeared in golden list of the reviewers from 2017-2023), Nature Scientific Reports, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,  IEEE Journal of the Electron Devices Society,  IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency, IEEE Access, Solid State Electronics, Semiconductor Science and Technology, Microelectronics Journal,  IETE Technical Review, IET Circuits, Devices, and Systems.
  • Science and Engineering Research Board, India Travel Grant 2019.
  • Indira Award by the Directorate of Education, Govt. of NCT of Delhi, 2007.

Educational Background
  • Joint Ph. D.-M.Tech., Electrical Engineering, Indian Institute of Technology Kanpur (2014-2020).
  • B.Tech., Electronics and Communication Engineering, Delhi Technological University (2010-2014).

2 Vacancies

Job Description

Students with a strong background and relevant qualifications will get an opportunity to work on and assist in the compact modeling, TCAD/Numerical and SPICE circuit simulations, and applications of AI for upcoming and advanced semiconductor device technologies (such as ferroelectric devices, cryogenic-CMOS, oxide semiconductor TFTs, high-voltage and RF devices, etc.).

Preferred Intern Education Level

Junior and Senior undergraduates, Master's, and PhD students

Skill sets or Qualities

Basic knowledge of semiconductor device physics and a positive attitude.